`timescale 1ns / 1ps
module dpi_interface_test;
    localparam DATA_WIDTH = 32;
    localparam ADDR_WIDTH = 32;

    logic clk;
    logic rst;
    logic write_en;
    logic read_en;
    logic req_valid;

    logic busy;
    logic ready;

    logic [ADDR_WIDTH-1:0] req_addr;
    logic [DATA_WIDTH-1:0] req_data;

    logic resp_valid;

    logic [ADDR_WIDTH-1:0] resp_addr;
    logic [DATA_WIDTH-1:0] resp_data;


    dpi_interface dpi_inter0 (
        .clk(clk),
        .rst(rst),
        .write_en(write_en),
        .read_en(read_en),
        .req_valid(req_valid),
        .busy(busy),
        .ready(ready),
        .req_addr(req_addr),
        .req_data(req_data),
        .resp_valid(resp_valid),
        .resp_addr(resp_addr),
        .resp_data(resp_data)
    );

    always begin 
        #5 clk = ~clk;
    end

    initial begin
        clk = 0;
        rst = 1;
        busy = 0;
        resp_valid = 0;
        # 10
        rst = 0;
        # 50
        busy = 1;
        # 50
        resp_valid = 1;
        resp_data = 32'h1234_5678;
        resp_addr = 32'h8000_0010;
        # 50
        resp_valid = 0;
        busy = 0;
        # 50
        busy = 1;
        # 50
        resp_valid = 1;
        resp_data = 32'h6666_5555;
        resp_addr = 32'h8000_0010;
        # 50
        busy = 0;
        # 50
        $stop;
    end

    always_ff @(posedge clk) begin
        $display("req = {addr = %x, data = %x},resp = {addr = %x,data = %x}", req_addr,req_data,resp_addr,resp_data);
    end

endmodule
